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KMM374S403CT
PC100 SDRAM MODULE
Revision History
Revision .0 (Feb. 1998)
- Input leakage Currents (Inputs / DQ) of Component level are changed. IIL(Inputs) : 5uA to 1uA, IIL(DQ) : 5uA to 1.5uA. - Cin to be measured at V DD = 3.3V, T A = 23C, f = 1MHz, V REF =1.4V 200 mV.
Revision .1 (Mar. 1998)
*AC Operating Condition is changed as defined : - VIH(max) = 5.6V AC. The overshoot voltage duration is 3ns. VIL(min) = -2.0V AC. The undershoot voltage duration is 3ns.
REV. 1 Mar. '98
KMM374S403CT
KMM374S403CT SDRAM DIMM
PC100 SDRAM MODULE
4Mx72 SDRAM DIMM with ECC based on 2Mx8, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION
The Samsung KMM374S403CT is a 4M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM374S403CT consists of eighteen CMOS 2M x 8 bit Synchronous DRAMs in TSOP-II 400mil package and a 1K or 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parellel for each SDRAM. The KMM374S403CT is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURE
* Performance range Max Freq. (Speed) KMM374S403CT-G8 125MHz (8ns) KMM374S403CT-GH 100MHz (10ns) KMM374S403CT-GL 100MHz (10ns) Burst Mode Operation Auto & Self Refresh Capability (4096 cycles / 64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst Length (1, 2, 4, 8 & Full page) Data Scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial Presence Detect with EEPROM PCB : Height(1,250mil), double sided component
* * * * *
* * *
PIN CONFIGURATIONS (Front Side / Back Side)
Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Front Pin Front Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ18 DQ19 VDD DQ20 NC *VREF CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP **SDA **SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 *A11 VDD CLK1 *A12 VSS CKE0 CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 Pin Back 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ50 DQ51 VDD DQ52 NC *VREF NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC **SA0 **SA1 **SA2 VDD 29 DQM1 CS0 30 31 DU 32 VSS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A10/AP 39 *BA1 40 VDD 41 VDD 42 CLK0 43 VSS 44 DU 45 CS2 46 DQM2 47 DQM3 48 DU 49 VDD 50 NC 51 NC 52 CB2 53 CB3 54 VSS 55 DQ16 56 DQ17
PIN NAMES
Pin Name A0 ~ A10/AP BA0 DQ0 ~ DQ63 CB0 ~ 7 CLK0 ~ CLK3 CKE0 ~ CKE1 CS0 ~ CS3 RAS CAS WE DQM0 ~ 7 VDD VSS *VREF SDA SCL SA0 ~ 2 WP DU NC Function Address Input (multiplexed) Select Bank Data Input / Output Check Bit (data-in / data-out) Clock Input Clock Enable Input Chip Select Input Row Address Storbe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Power Supply for Reference Serial Data I/O Serial Clock Address in EEPROM Write Protection Dont use No Connection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 1 Mar. '98
KMM374S403CT
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System Clock Chip Select
PC100 SDRAM MODULE
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+t SS prior to valid command. Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with Enables row access & precharge. RAS low. CAS low.
CKE
Clock Enable
A0 ~ A10/AP BA0 RAS CAS WE DQM0 ~ 7 DQ0 ~ 63 CB0 ~ 7 WP VDD/VSS
Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Check bit Write Protection Power Supply/Ground
Latches column addresses on the positive going edge of the CLK with Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Check bits for ECC.
WP pin is connected to V CC. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write - protected. Power and ground for the input buffers and the core logic.
REV. 1 Mar. '98
KMM374S403CT
FUNCTIONAL BLOCK DIAGRAM
CS1 CS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
PC100 SDRAM MODULE
* *
DQM4
* DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
* DQM CS
U5
CS
U0
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U9 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U14
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
* DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
* DQM CS
U6
CS
U1
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U10 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQM
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS3 CS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U2
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
DQM6 U11 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
* DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U7
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U16
* DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
* CS
U3
*
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U12
* DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U8
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U17
* DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U4
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
U13
Serial PD VDD SCL SDA A0 A1 A2 * WP 47
A0 ~ An, BA0 RAS CAS WE CKE0 10 DQn VDD Vss * * * *
SDRAM U0 ~ U17 SDRAM U0 ~ U17 SDRAM U0 ~ U17 SDRAM U0 ~ U17 SDRAM U0 ~ U8 CKE1
SA0 SA1 SA2 10K * SDRAM U9 ~ U17 10 CLK0/1/2/3 * * 3.3pF *1 To all SDRAMs *
*
U1/U3/U0/U4 U6/U7/U5/U8 U10/U12/U9/U13 U15/U16/U14/U17 U2/U11
Every DQpin of SDRAM
Two 0.1uF Capacitors per each SDRAM
*1 : For 4 loads, CLK2 & CLK3 only.
REV. 1 Mar. '98
KMM374S403CT
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on V DD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS
PC100 SDRAM MODULE
Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 18 50 Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V Parameter Supply voltage Input logic high votlage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current(Inputs) Input leakage current (I/O pins) Symbol VDD, VDDQ VIH VIL VOH VOL IIL IIL
SS
= 0V, T A = 0 to 70 C) Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 18 3 Unit V V V V V uA uA 1 2 IOH = -2mA IOL = 2mA 3 3,4 Note
Min 3.0 2.0 -0.3 2.4 -18 -3
Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE
(VDD = 3.3V, T A = 23C, f = 1MHz, V REF =1.4V 200 mV) Pin Symbol CADD CIN CCKE CCLK CCS CDQM COUT1 COUT2 Min 65 65 40 30 30 15 10 10 Max 95 95 60 40 40 25 20 20 Unit pF pF pF pF pF pF pF pF
Address (A0 ~ A10/AP, BA0) RAS, CAS, WE CKE (CKE0) Clock (CLK0, CLK2) CS (CS0, CS2) DQM (DQM0 ~ DQM7) DQ (DQ0 ~ DQ63) CB (CB0 ~ CB7)
REV. 1 Mar. '98
KMM374S403CT
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T Parameter Symbol
A
PC100 SDRAM MODULE
= 0 to 70 C) CAS Latency Version -8 1,035 -H 990 18 18 270 mA 72 36 18 450 270 3 2 1,215 990 1,110 1,110 990 18 1,110 mA 990 mA mA 2 1 mA mA -L 990 mA 1 Unit Note
Test Condition Burst Length =1 t RCtRC(min) I OL = 0 mA CKEVIL(max), t CC = 15ns CKE & CLK VIL(max), t CC =
Operating Current (One Bank Active) Precharge Standby Current in power-down mode
ICC1 ICC2P ICC2PS ICC2N
mA
Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode ICC3P ICC3PS ICC3N ICC3NS
CKEVIH(min), CSVIH(min), t CC = 15ns Input signals are changed one time during 30ns CKEVIH(min), CLK VIL(max), t CC = Input signals are stable CKEVIL(max), t CC = 15ns CKE & CLK VIL(max), t CC = CKEVIH(min), CSVIH(min), t CC = 15ns Input signals are changed one time during 30ns CKEVIH(min), CLK VIL(max), t CC = Input signals are stable I OL = 0 mA Page Burst 2Banks Activated t CCD = 2CLKs tRCtRC(min) CKE0.2V
mA
Active Standby Current in non power-down mode (One Bank Active)
Operating Current (Burst Mode) Refresh Current Self Refresh Current
ICC4
ICC5 ICC6
Note : 1. Measured with outputs open. 2. Refresh period is 64ms.
REV. 1 Mar. '98
KMM374S403CT
AC OPERATING TEST CONDITIONS
Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V
PC100 SDRAM MODULE
(VDD = 3.3V 0.3V, TA = 0 to 70 C) Value 2.4 / 0.4 1.4 tr / tf = 1 / 1 1.4 See Fig. 2
Vtt=1.4V
Unit V V ns V
1200 Output 870 * * * 50pF VOH (DC) = 2.4V, I OH = -2mA VOL (DC) = 0.4V, I OL = 2mA Output Z0=50 *
50
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol -8 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD(min) 68 16 20 20 48 Version -H 20 20 20 50 100 70 1 1 1 1 2 1 70 -L 20 20 20 50 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2 2 2 3 4 1 1 1 1 Unit Note
CAS Latency=3 CAS Latency=2
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
REV. 1 Mar. '98
KMM374S403CT
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Refer to the individual componenet, not the whole module.
Parameter CAS Latency=3 CAS Latency=2 CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 3 3 2 1 1 6 6 tSAC Symbol Min CLK cycle time tCC 8 12 6 6 3 3 3 3 2 1 1 -8 Max 1000 Min 10 10 -H
PC100 SDRAM MODULE
-L Max 1000 6 6 3 3 3 3 2 1 1 6 6 6 7 Min 10 12 6 7 Max 1000
Unit
Note
ns
1
ns
1, 2
ns ns ns ns ns ns ns
2 3 3 3 3 2
Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
REV. 1 Mar. '98
KMM374S403CT
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
KMM374S403CT-G8
Frequency 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) CAS Latency 3 3 2 2 2 tRC 68ns 9 7 6 6 6 tRAS 48ns 6 5 4 4 4 tRP 20ns 3 2 2 2 2 tRRD 16ns 2 2 2 2 2
PC100 SDRAM MODULE
(Unit : number of clock) tRCD 20ns 3 2 2 2 2 tCCD 8ns 1 1 1 1 1 tCDL 8ns 1 1 1 1 1 tRDL 8ns 1 1 1 1 1
KMM374S403CT-GH
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 2 2 2 2 2 tRC 70ns 7 6 6 5 5 tRAS 50ns 5 5 4 4 3 tRP 20ns 2 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 20ns 2 2 2 2 2 tCCD 10ns 1 1 1 1 1
(Unit : number of clock) tCDL 10ns 1 1 1 1 1 tRDL 10ns 1 1 1 1 1
KMM374S403CT-GL
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 3 2 2 2 2 tRC 70ns 7 6 6 5 5 tRAS 50ns 5 5 4 4 3 tRP 20ns 2 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 20ns 2 2 2 2 2 tCCD 10ns 1 1 1 1 1
(Unit : number of clock) tCDL 10ns 1 1 1 1 1 tRDL 10ns 1 1 1 1 1
REV. 1 Mar. '98
KMM374S403CT
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit L H H
CKEn-1 CKEn CS RAS CAS
PC100 SDRAM MODULE
WE DQM BA0 A10/AP A9 ~ A0 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP CODE X
1, 2 3 3
X X X V V
X Row Address L H
Column Address (A0~A8) Column Address (A0~A8)
3 3
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection Both Banks Clock Suspend or Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
L L
4 4, 5 4 4, 5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X
X H L
L H H
H
H L
X V
X V X X 7
X
H L
X H
X H
X H
X
(V=Valid, X=Don t Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code A0 ~ A10/AP, BA 0 : Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA0 : Bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A10/AP is "High" at row precharge, BA 0 is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the assoiated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
REV. 1 Mar. '98
KMM374S403CT
PACKAGE DIMENSIONS
PC100 SDRAM MODULE
Units : Inches (millimeters)
5.250 (133.350) 0.118 (3.000) 0.387 0.062 (9.84 1.59) 0.175 (4.45) 5.014 (127.350)
0.089 (2.26) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100 )
1.375 (34.925)
0.118 (3.000)
.118DIA .004 (3.000DIA .100) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830) 4.550 (115.57)
0.250 (6.350) 2.150 (54.61)
0.100Min (2.540Min)
A
B
C
0.700 (17.780)
0.150Max (3.81Max) (5.08 Min) 0.200 Min
0.050 0.0039 (1.270 0.10)
0.250 (6.350 )
0.250 (6.350 )
(2.540 Min)
0.100 Min
0.039 .002 (1.000 .050)
0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100)
0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100)
0.010Max (0.250 Max) 0.050 (1.270 )
Detail A
Detail B
Detail C
Tolerances : .005(.13) unless otherwise specified The used device is 2Mx8 SDRAM, TSOP SDRAM Part No. : KM48S2020CT
REV. 1 Mar. '98

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